Test & Yield
Management Solutions

yieldWerx offers product and test engineers a collection of reliable, easily manageable, and robust tools that help improve productivity, improve yield, and reduce defects in the assembly line. yieldWerx converts semiconductor test data files into comprehensive reports, which provides graphical and statistical representation of data and reduces defect analysis cycle time for test engineers.

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yieldWerx Process Details

yieldWerx offers product and test engineers a collection of reliable, easily manageable, and robust tools that help improve productivity, improve yield, and reduce defects in the assembly line. yieldWerx converts semiconductor test data files into comprehensive reports, which provides graphical and statistical representation of data and reduces defect analysis cycle time for test engineers.

yieldWerx provides a suite of test data acquisition, analysis and reporting solutions for semiconductor companies/design houses and engineering groups. With easy access to production data, engineering data from manufacturing processes, wafer probe data , final test data as well as other external data sources

yieldWerx Components

Lot Genealogy Tool:
Tie in lot history and genealogy data together with the test data so an engineer can being their analysis from anywhere in the lots history.

Automated Data Loaders:
Load data real time or on a periodic basic with functionality to auto correct missing data, implement rules based on work center, device, test algorithm and lot numbers.

Automatic Report Generation Module:
Execute commonly accessed/needed report on any time basis with the results being published to select locations.

Yield Monitoring

yieldWerx provides a lot of reports to monitor yield. It includes yield by test program, device or via a single key click monitor the yield trends. The next release of yieldWerx will introduce real time alerts, in that the user can set control limits and if the yield drops below a certain % then registered users will get email notifications as to what lots have a yield issue.

Prober to Prober Analysis
Prober Card to Prober Card Analysis
Load Card to Load Card Analysis
Site to Site Analysis

Smart Probe

Wafer Map Layout & Real Time Data Collection/Control. The savings, reduction in test times, ability to monitor and detect anomalies and issues quickly, react to hardware failures and save valuable data and continue probing from where you left off and more – can very quickly mean many thousands of dollars/millions of dollars of savings for large test floors.

Ability to probe the back and front of wafer (e.g. LED devices) – in either order and then only probe the die that passed from the first pass.

Probe only predefined die and skip die, to avoid probe card damage e.g. in the case of  bumped die where you don't want to touch down and probe die with bad bumps.